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w78c54 8-bit microcontroller publication release date: december 1997 - 1 - revision a2 general description the w78c54 is a derivative of the w78c52 microcontroller family that provides extended internal rom. the chip has 16k bytes of mask rom and 256 bytes of ram. this device provides an enhanced architecture that makes it more powerful and suitable for a variety of applications for general control systems. it provides on-chip 16kb mask rom to accommodate large program codes, 256-bytes of non-volatile on-chip ram, four 8-bit i/o ports, one 4-bit i/o port, three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator clock circuits. features dc to 40 mhz extensive operating frequency 256-byte on-chip scratch pad ram 16k-byte on-chip mask rom 64k-byte address space for external program memory 64k-byte address space for external data memory three 16-bit timer/counters four 8-bit bit-addressable i/o ports one extra 4-bit bit-addressable i/o port, additional int2/ int3 (available on 44-pin plcc/qfp package) eight-source, two priority-level interrupts low emi emission mode built-in programmable power-saving modes - idle mode & power-down mode packages: - dip 40: w78c54-16/24/40 - plcc 44: w78c54p-16/24/40 - qfp 44: W78C54F-16/24/40 - tqfp 44: w78c54m-16/24/40
w78c54 - 2 - pin configurations vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78c54) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78c54p) 44-pin qfp/tqfp (w78c54f/w78c54m) 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v c c a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3. txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v c c a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p 4 . 0 / i n t 3 , p 4 . 2 p4.1 p4.1 p 4 . 0 int2, p4.3 int2, p4.3 / i n t 3 , p 4 . 2
w78c54 publication release date: december 1997 - 3 - revision a2 pin description symbol type descriptions ea i external access enable: this pin forces the processor to execute out of external rom. the rom address and data will not be present on the bus if the ea pin is high and the program counter is within the 16 kb area. otherwise they will be present on the bus. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o h address latch enable: ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. an ale pulse is omitted during external data memory accesses. rst i l reset: a high on this pin for two machine cycles while the oscillator is running resets the device. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal oscillator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 - p0.7 i/o d port 0: function is the same as that of the standard 8052. p1.0 - p1.7 i/o h port 1: function is the same as that of the standard 8052. p2.0 - p2.7 i/o h port 2: function is the same as that of the standard 8052. p3.0 - p3.7 i/o h port 3: function is the same as that of the standard 8052. p4.0 - p4.3 i/o h port 4: a 4-bit bi-directional parallel port and bit-addressable with internal pull-ups. pin p4.3 and p4.2 have alternative function as external interrupt (int2/int3) source input. int2 (p4.3) i h external interrupt 2: an extra interrupt input source. it cascades to pin p4.3 internally. int3 (p4.2) i h external interrupt 3: an extra interrupt input source. it cascades to pin p4.2 internally. * note : type i: input, o: output, i/o: bi-directional, h: pull-high, l: pull-low, d: open drain
w78c54 - 4 - block diagram p3.0 ~ p3.7 p1.0 ~ p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale gnd vcc rst xtal2 oscillator interrupt psw 16kb rom instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 256 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 ~ p4.3 port 4 port 0 port 2 p2.0 ~ p2.7 p0.0 ~ p0.7 int2 int3 figure 2. architecture of the w78c54
w78c54 publication release date: december 1997 - 5 - revision a2 functional description the w78c54 is pin-to-pin compatible with the w78c52, except that the internal 8k mask rom has been replaced with 16k of internal mask rom. the processor supports 111 different opcodes and references both 64k program address space and 64k data storage space. clock the w78c54 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used. this makes the w78c54 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78c54 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal is connected across pins xtal1 and xtal2. in addition, a load capacitance of 30 pf (typically) must be connected from each pin to ground. resistor must also be connected from xtal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the external clock signal should have an input one level greater than 3.5 volts. power management idle mode the idle mode is entered by setting the idle bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode when the pd bit of the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks are stopped, including the oscillator. the only way to exit power-down mode is by a reset. reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to deglitch the reset line when the w78c54 is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. new defined peripheral in order to be more suitable for i/o, an extra 4-bit bit-addressable port p4 and two external interrupt int2, int3 has been added to either the plcc or qfp 44 pin package. and description follows:
w78c54 - 6 - 1. int2 / int3 two additional external interrupts, int2 and int3, whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb (/clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. 2. port4 another bit-address port p4 is also available except only 4 bits (p4<3:0>) can be used. this port address is located at 0d8h with the same function as that of port p1,except the p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources (int2/int3). example: p4 reg 0d8h mov p4, #0ah ; output data "a" through p4.0 - p4.3. mov a, p4 ; read p4 status to accumulator. setb p4.0 ; set bit p4.0 clr p4.1 ; clear bit p4 .1 reduce emi emission because of the large on-chip mask-rom, when a program is running in internal rom space, the ale will be unused. the transition of ale will cause noise, so it can be turned off to reduce the emi emission if it is useless. turning off the ale signal transition only requires setting the bit 0 of the auxr sfr, which is located at 08eh. when ale is turned off, it will be reactivated when the program accesses external rom/ram data or jumps to execute an external rom code. the ale signal will turn off again after it has been completely accessed or the program returns to internal rom code space.. pof flag the power-off-reset flag is set by on-chip circuitry when the v cc level rises from 0 to 5v. the pof bit can be set/cleared by software allowing a user to determine if the reset is the result of a power-on or a warm up by external reset. to avoid effect of pof flag, the power voltage must remain above 3v. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a special feature of the w78c52c: it is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto- reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1.
w78c54 publication release date: december 1997 - 7 - revision a2 descriptions of the special function registers (sfrs) sym. definition addr. msb bit address, symbol lsb reset b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 00000000b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) (e2) (e1) (e0) 00000000b p4* port 4 d8h - - - - (db) int2 (da) int3 (d9) (d8) xxxx0000b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) - (d0) p 00000000b th2 t2 reg. high cdh 00000000b tl2 t2 reg. low cch 00000000b rcap2h t2 capture high cbh 00000000b rcap2l t2 capture low cah 00000000b t2con timer 2 control c8h (cf) tf2 (ce) exf2 (cd) rclk (cc) tclk (cb) exen2 (ca) tr2 (c9) c/t2 (c8) cp/rl2 00000000b xicon* external interrupt control c0h (c7) px3 (c6) ex3 (c5) ie3 (c4) it3 (c3) px2 (c2) ex2 (c1) ie2 (c0) it2 00000000b ip interrupt priority b8h - - pt2 ps pt1 px1 pt0 px0 xx000000b p3 port 3 b0h (b7) rd (b6) wr (b5) t1 (b4) t0 (b3) int1 (b2) int0 (b1) txd (b0) rxd 11111111b ie interrupt enable a8h (af) ea (ae) - (ad) et2 (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 00000000b p2 port 2 a0h (a7) a15 (a6) a14 (a5) a13 (a4) a12 (a3) a11 (a2) a10 (a1) a9 (a0) a8 11111111b sbuf serial buffer 99h xxxxxxxxb scon* serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 00000000b p1* port 1 90h (97) (96) (95) (94) (93) (92) (91) t2ex (90) t2 11111111b auxr* auxiliary 8eh - - - - - - - ao xxxxxxx0b th1 timer high 1 8dh 00000000b th0 timer high 0 8ch 00000000b tl1 timer low 1 8bh 00000000b tl0 timer low 0 8ah 00000000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00000000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 00000000b pcon* power control 87h smod smod0 - pof+ gf1 gf0 pd idl 00xxxx00b dph data pointer high 83h 00000000b dpl data pointer low 82h 00000000b sp stack pointer 81h 00000111b p0 port 0 80h (87) (86) (85) (84) (83) (82) (81) (80) 11111111b
w78c54 - 8 - note: in column bit_address, symbol , containing ( ) item means the bit address. * sfrs modified or added to the w78c52. + reset value depends on reset condition. w78c54 sfrs address location map: f8 ff f0 + b f7 e8 ef e0 + acc e7 d8 +p4 df d0 + psw d7 c8 +t2con rcap2l rcap2h tl2 th2 cf c0 +xicon c7 b8 + ip bf b0 + p3 b7 a8 + ie af a0 + p2 a7 98 + scon sbuf 9f 90 + p1 97 88 + tcon tmod tl0 tl1 th0 th1 auxr 8f 80 +p0 sp dpl dph pcon 87 notes: 1. + sfr is bit-addressable. 2. is additional defined function. power-off flag ***pcon - power control (87h) smod smod0 - pof gf1 gf0 pd idl smod: double baud rate bit. when set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2, 3. smod0: enable fe bit in scon. this bit is an alternative switch of sm0 and fe (frame error) bit. when set to a 1, scon.7 means a fe bit, otherwise a sm0 bit. pof: power off flag. bit is set by hardware when power on reset. it can be cleared by software to determine chip reset is a warm boot or cold boot. gf1, gf0: these two bits are general-purpose flag bits for the user. pd: power down mode bit. set it to enter power down mode. idl: idle mode bit. set it to enter idle mode. the power-off flag is located at pcon.4. this bit is set when v dd has been applied to the part. it can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
w78c54 publication release date: december 1997 - 9 - revision a2 * interrupts ***ie - interrupt enable (a8h) ea - et2 es et1 ex1 et0 ex0 ea: lobal interrupt enable flag et2: timer 2 overflow interrupt enable es: serial port interrupt enable ex1: external interrupt 1 enable et1: timer 1 overflow interrupt enable ex0: external interrupt 0 enable ***ip - interrupt priority (b8h) - - pt2 ps pt1 px1 pt0 px0 pt2: timer 2 interrupt priority high if set ps: serial port priority high if set pt1: timer 1 interrupt priority high if set px1: external interrupt 1 priority high if set pt0: timer 0 interrupt priority high if set px0: external interrupt 0 priority high if s et ***xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatical ly by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software the w78c54 supports an eight-source and a four-priority-level interrupt architectures. besides the sfrs of ip and ie to control the six-source of the standard 8052 interrupt functions. there is an another sfr (xicon) to control the extra two-source of the external interrrupt (int2 and int3). this priority scheme is formed by combining iph with ip to determine the priority of each interrupt. except the int2 and int3, they are not defined in ip sfr but in xicon.
w78c54 - 10 - following tables show the interrupt informations and priority definitions. eight-source interrupt informations: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.it0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.it1 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.ex2 xicon.it2 external interrupt 3 3bh 7 (lowest) xicon.ex3 xicon.it3 *timer/counter ***tl0, th0, tl1, th1, tl2, th2, rcap2l, rcap2h ***tmod - timer 0, 1 mode (89h) gate c//t m1 m0 gate c//t m1 m0 timer0 timer1 gate: gating control. when set, timer/counter x is enabled only while intx pin is high and trx control pin is set. when cleared, timer x is enabled whenever the trx conrol bit i s set. c//t: timer or counter selector. cleared for timer operation. set for counter operation. m1 m0: operating mode 0 0: 13-bit timer/counter. 0 1: 16-bit timer/counter. 1 0: 8-bit auto-reload timer/counter. thx holds a value which is to be reloaded into tlx each time it overflows. 1 1: timer 0: tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. timer 1: timer/counter 1 stopped. ***tcon - timer 0, 1 control (88h) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1: timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine.
w78c54 publication release date: december 1997 - 11 - revision a2 tr1: timer 1 run control bit. set/cleared by software to turn timer/counter on or off. tf0: timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr0: timer 0 run control bit. set/cleared by software to turn timer/counter on or off. ie1: interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it1: interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. ie0: interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it0: interrupt 0 type control bit. set/cleared by software to specify falling edg e/low level triggered external interrupt. ***t2con - timer 2 control (c8h) tf2 exf2 rclk tclk exen2 tr2 c//t cp//rl2 tf2: timer 2 overflow flag. set by a timer 2 overflow and must be cleared by software. tf2 will not be set when rclk = 1 or tclk = 1. exf2: timer2 external flag. set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt rou tine. exf2 must be cleared by software. rclk: receive clock flag. rclk = 1 causes the serial port to use timer 2 overflow pulses for its receive clock in mode 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk: transmit clock flag. tclk = 1 causes the serial port to use timer 2 overflow pulses for its transmit clock in mode 1 and 3. tclk = 0 causes timer 1 overflow to be used for the transmit clock. exen2: timer 2 external enable flag. exen2 = 1 allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2: tr2 = 1/0: turns on/off timer 2. c//t: timer or counter select. set 1/0 for external event counter(falling edge triggered)/inter timer. cp//rl2: capture/reload flag. *reduced emi mode the ao bit in the auxr register, when set, disables the ale output. ***auxr - auxiliary register (8eh) - - - - - - - ao ao: turn off ale output.
w78c54 - 12 - absolute maximum ratings parameter symbol min. max. unit dc power supply v cc - v ss -0.3 +7.0 v input voltage v in v ss -0.3 v cc +0.3 v operating temperature t a 0 70 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (v dd - v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) parameter sym. specification unit test conditions min. max. operating voltage v dd 4.5 5.5 v operating current i dd - 20 ma no load v dd = 5.5v idle current i idle - 6 ma idle mode v dd = 5.5v power down current i pwdn - 50 m a power-down mode v dd = 5.5v input current p1, p2, p3, p4 i in1 -50 +10 m a v dd = 5.5v v in = 0v or v dd input current rst i in2 -10 +300 m a v dd = 5.5v 0 < v in < v dd input leakage current p0, ea i lk -10 +10 m a v dd = 5.5v 0v < v in < v dd logic 1 to 0 transition current p1, p2, p3, p4 i tl [*4] -500 -200 m a v dd = 5.5v v in = 2.0v input low voltage p0, p1, p2, p3, p4, ea v il1 0 0.8 v v dd = 4.5v input low voltage rst v il2 0 0.8 v v dd = 4.5v input low voltage xtal1[*4] v il3 0 0.8 v v dd = 4.5v
w78c54 publication release date: december 1997 - 13 - revision a2 dc characteristics, continued parameter sym. specification unit test conditions min. max. input high voltage p0, p1, p2, p3, p4, ea v ih1 2.4 v dd +0.2 v v dd = 5.5v input high voltage rst v ih2 3.5 v dd +0.2 v v dd = 5.5v input high voltage xtal1 [*4] v ih3 3.5 v dd +0.2 v v dd = 5.5v output low voltage p1, p2, p3, p4 v ol1 - 0.45 v v dd = 4.5v i ol = +2 ma output low voltage p0, ale, psen [*3] v ol2 - 0.45 v v dd = 4.5v i ol = +4 ma sink current p1, p2, p3, p4 i sk1 4 8 ma v dd = 4.5v vs = 0.45v sink current p0, ale, psen i sk2 10 14 ma v dd = 4.5v vs = 0.45v output high voltage p1, p2, p3, p4 v oh1 2.4 - v v dd = 4.5v i oh = -100 m a output high voltage p0, ale, psen [*3] v oh2 2.4 - v v dd = 4.5v i oh = -400 m a source current p1, p2, p3, p4 i sr1 -120 -180 m a v dd = 4.5v vs = 2.4v source current p0, ale, psen i sr2 -10 -14 ma v dd = 4.5v vs = 2.4v notes: *1. rst pin is a schmitt trigger input. rst has internal pull-low resistors of about 30 k w . *3. p0, ale and /psen are tested in the external access mode. *4. xtal1 is a cmos input. *5. pins of p1, p2, p3, p4 can source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in approximates to 2v. ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.8 micron cmos process when using 2 and 4 ma output buffers.
w78c54 - 14 - clock input waveform t t xtal1 f ch cl op, t cp continued parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle external program memory fetch cycle (see figure 6) parameter symbol min. typ. max. uint notes address valid to ale low t aas 1t cp - d - - ns address hold after ale low t aah 1t cp - d - - ns 1 ale low to psen low t apl 1t cp - d 1t cp 1t cp + d ns psen low to data valid t pda - - 2t cp ns 2 data hold after psen high t pdh 0 - 1t cp ns 3 data float after psen high t pdz 0 - 1t cp ns ale pulse width t alw 2t cp - d 2t cp 2t cp + d ns 4 psen pulse width t psw 3t cp - d 3t cp 3t cp + d ns 4 notes: 1. p00-p07, p20-p27 remain stable through entire memory cycle. 2. memory access time is 3 tcp. 3. data has been latched internally prior to /psen going high. 4. d is 20 ns (due to buffer driving delay and wire loading).
w78c54 publication release date: december 1997 - 15 - revision a2 data read cycle external data memory read cycle (see figure 7) parameter symbol min. typ. max. uint notes ale low to rd low t dar 3 tcp- d 3 tcp 3 tcp+ d ns 1, 2 rd low to data valid t dda - - 4 tcp ns 1 data hold after rd high t ddh 0 - 2 tcp ns data float after rd high t ddz 0 - 2 tcp ns rd pulse width t drd 6 tcp- d 6 tcp 6 tcp+ d ns 2 notes: 1. data memory access time is 5 tcp. 2. d is 20 ns (due to buffer driving delay and wire loading. data write cycle external data memory write cycle (see figure 8) parameter symbol min. typ. max. uint note ale low to wr low t daw 3 tcp- d 3 tcp 3 tcp+ d ns * data valid to wr low t dad 1 tcp- d - - ns data hold after wr high t dwd 1 tcp- d - - ns wr pulse width t dwr 6 tcp- d 6 tcp 6 tcp+ d ns * *note: d is 20 ns (due to buffer driving delay and wire loading) port access cycle port access cycle (see figure 9) parameter symbol min. typ. max. uint port input setup to ale low t pds 1tcp - - ns port input hold after ale low t pdh 0 - - ns port output to ale high t pda 1tcp- d - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference.
w78c54 - 16 - timing waveforms program fetch cycle xtal1 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale talw psen tapl tpsw taas p2 pch out pch out p0 pcl out pcl out taah code tpda tpdh,tpdz code code pcl out pcl out pch out pch out code figure 6. external program memory fetch cycle data read cycle xtal1 s4 s5 s6 s1 s2 s3 s4 s5 ale psen p2 dph or p2 sfr out p0 tdar data dpl or ri out tddh,tddz /rd tdrd tdda figure7. external data memory read cycle
w78c54 publication release date: december 1997 - 17 - revision a2 timing waveforms, continued data write cycle xtal1 s4 s5 s6 s1 s2 s3 s4 s5 ale psen p2 dph or p2 sfr out p0 tdaw data dpl or ri out tdwd wr tdwr tdad figure 8. external data memory write cycle port access cycle xtal1 ale port input sample output clock s5 s6 s1 data out data in tpds tpdh tpda figure 9. port access cycle
w78c54 - 18 - application circuit expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 35 x1 21 x2 20 reset 10 int0 14 int1 15 t0 16 t1 17 p1.0 2 p1.1 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 24 25 26 27 28 19 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 18 psen 32 ale 33 txd 13 rxd 11 w78c54 vcc 10u 8.2k vcc crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 9 29 30 43 42 41 40 31 figure a table 1 shows the typical values of off-chip components to configure the on-chip oscillator. table 1. off-chip components list crystal freq. c1 c2 r 12 mhz 30 pf 30 pf - 16 mhz 30 pf 30 pf - 20 mhz 15 pf 15 pf - 24 mhz 15 pf 15 pf - 33 mhz 10 pf 10 pf 6.8 k w 40mhz 5 pf 5 pf 4.3 k w notes: 1. refer to figure 10 for c1, c2 and r. 2. it is recommended that an oscillator be used as external clock source when operating freq. is above 35mhz. apply the external clock signal to xtal1, and leave xtal2 float, as shown in figure 10.
w78c54 publication release date: december 1997 - 19 - revision a2 application circuit, continued expanded external d ata memory and oscillator 10u 8.2k vcc oscillator vcc ea 35 x1 21 x2 20 reset 10 int0 14 int1 15 t0 16 t1 17 p1.0 9 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 29 p2.1 30 p2.2 31 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 19 wr 18 psen 32 ale 33 txd 13 rxd 11 w78c54 43 38 37 36 42 41 40 39 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad7 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 ad0 ad1 ad2 ad3 ad4 ad5 ad6 3 4 7 8 13 14 17 q6 d7 18 q7 a0 a1 a2 a3 a4 a5 a6 a7 2 5 6 9 12 15 16 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 ce a8 a9 a10 a11 a12 a13 a14 gnd a0 10 20 a1 a2 a3 a4 a5 a6 a7 9 8 7 6 5 4 3 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 2 gnd 22 27 oe wr 20256 figure b
w78c54 - 20 - package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2 44-pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a e h e l y b c d a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q
w78c54 publication release date: december 1997 - 21 - revision a2 package dimensions, continued 44-pin qfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- q 2 q 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905 44-pin tqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.200 0.090 0.008 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm --- --- 0.047 0.002 0.037 0.0039 0.039 0.013 0.041 0.015 0.95 0.22 0.05 1.00 0.32 1.05 0.38 0.390 0.018 0.039 0.003 0 7 0.394 0.024 0.398 0.030 9.9 0.80 0.45 1.00 10.00 0.60 10.1 0.75 0.398 0.394 0.390 0.476 0.472 0.468 12.10 12.00 11.90 10.1 10.00 9.9 7 0 0.08 0.031 0.004 0.006 0.10 0.15 --- --- --- --- 1.20 a b c d e h d h e l y a a l 1 1 2 e q 2 q 0.025 0.036 0.635 0.952 0.476 0.472 0.468 12.10 12.00 11.90 --- --- --- ---
w78c54 - 22 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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